Increasingly sophisticated computer systems permit users to perform an expanding variety of computing tasks at faster and faster rates. The size of the memory and the memory access speed bear heavily upon the overall speed of the computer system.
One principle underlying data storage in magnetic media (main or mass storage) is the ability to change and/or reverse the relative orientation of the magnetization of a storage data bit, (i.e. the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and/or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle, the higher its coercivity.
Known magnetic memory cells may be tunneling magneto-resistance memory cells (TMR), giant magneto-resistance memory cells (GMR), or colossal magneto-resistance memory cells (CMR). These types of magnetic memory are commonly referred to as spin valve memory cells (SVM). FIGS. 1A and 1B provide a perspective view of a typical prior art magnetic memory cell having two conductors.
As shown in prior art FIGS. 1A and 1B, a magnetic spin valve memory (SVM) cell 101 generally includes a data layer 103 which may alternatively be called a storage layer or bit layer, a reference layer 105 and an intermediate layer 107 between the data layer 103 and the reference layer 105. The data layer 103, the reference layer 105 and the intermediate layer 107 can be made from one or more layers of material.
Where wiring layers are provided in a grid of rows and columns, electrical current and magnetic fields may be applied to the SVM cell 101 via electrically conductive row conductor 109 and electrically conductive column conductor 111. It is understood and appreciated that, as used herein, the terms row and column conductor have been selected for ease of discussion. Under appropriate circumstances, these labels may be reversed and/or otherwise substituted for such titles as word line and bit line.
Using photolithographic techniques, the single SVM cell 101 shown in FIGS. 1A and 1B is typically combined with a plurality of other substantially identical SVM cells. In a typical MRAM device, the SVM cells are arranged in a cross-point array. Parallel conductive columns (column 1, 2, 3 . . . i not shown), also referred to as word lines, cross parallel conductive rows (row A, B, C . . . i not shown), also referred to as bit lines. The traditional principles of column and row arrays dictate that any given row will only cross any given column once.
An SVM cell is placed at each intersecting cross-point between a row and a column. By selecting a particular row (B) and a particular column (3), any one memory cell positioned at their intersection (B, 3) can be isolated from any other memory cell in the array. Such individual indexing is not without complexities.
The data layer 103 is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization M1 that may be altered in response to the application of an external magnetic field or fields. More specifically, the orientation of magnetization M1 of the data layer 103 representing the logic state can be rotated (switched) from a first orientation 117, as in FIG. 1A, representing a logic state of “0”, to a second orientation 119, as in FIG. 1B representing a logic state of “1”, and/or vice versa.
The reference layer 105 is usually a layer of magnetic material in which an orientation of magnetization M2 is “pinned”, as in fixed, in a predetermined direction or pinned orientation 121. The direction is predetermined and established by conventional microelectronic processing steps employed in the fabrication of the magnetic memory cell.
The data layer 103 and reference layer 105 may be thought of as stacked bar magnets, each long on an X axis 113 and short on a Y axis 115. The magnetization of each layer has a strong preference to align along the easy axis, generally the long X axis 113. The short Y axis 115 is generally the hard axis. Alignment of the orientation of magnetization M1 of the data layer 103 in the first orientation 117 or second orientation 119 requires substantially the same amount of energy, and thus requires the same external magnetic field, to align the spins of the atomic particles in either direction.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization M1 in the data layer 103 and M2 of the reference layer 105 (117 to 121 as shown in FIG. 1A or 119 to 121 as shown in FIG. 1B). For example, when an electrical potential bias is applied across the data layer 103 and the reference layer 105 in an SVM cell 101, electrons migrate between the data layer 103 and the reference layer 105 through the intermediate layer 107. The intermediate layer 107 is typically a thin dielectric layer, which is commonly referred to as a tunnel barrier layer. The phenomenon that causes the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling, or spin tunneling.
The logic state may be determined by measuring the resistance of the SVM cell 101. For example, if the orientation 119 of the magnetization M1 in the data layer 103 is parallel to the pinned orientation 121 of magnetization in the reference layer 105, the SVM cell 101 will be in a state of low resistance, R (see FIG. 1B). If the first orientation 117 of the magnetization M1 in the data layer 103 is anti-parallel (opposite) to the pinned orientation 121 of magnetization in the reference layer 105, the SVM cell 101 will be in a state of high resistance, R+ΔR (see FIG. 1A). The orientation of M1, and therefore the logic state of the SVM cell 101, may be read by sensing the resistance of the SVM cell 101.
Generally speaking, the smaller the magnetic particle, the higher its coercivity. A large coercivity is generally undesirable as it requires a greater magnetic field to facilitate switching, which in turn requires a greater power source and potentially larger conductors. Providing a large power source and large conductors is generally at odds with attempts to reduce the necessary size of components, and therefore permit larger memory stores in smaller and smaller spaces.
In addition, the coercivity of a magnetic particle may be affected by temperature. Generally as temperature increases, coercivity decreases. With respect to MRAM and SVM cells, elevating the temperature of an SVM cell may indeed reduce the coercivity. The heating of an SVM cell 101 within an MRAM array may generally be accomplished through either of two forms.
The first form is generalized heating where the desired SVM cell is heated collectively along with unselected/undesired SVM cells. In the most basic setting, the entire memory array is heated. Such generalized heating reduces the coercivity of unselected SVM cells along with the selected SVM cell and therefore may permit inadvertent and undesirable switching of unselected SVM cells, commonly referred to as half-select errors.
The second form is selected heating where the desired SVM cell is heated independently of the unselected SVM cells within the memory. Such selected heating is traditionally accomplished with the use of movable heating probes or other external heaters which can provide a localized heat directly to a selected SVM cell, additional heating conductors and or elements placed proximately to the SVM cells of the memory, and/or the application of a heating pulse briefly passed through a selected SVM cell. The heating of a selected SVM cell 101 may therefore lower the coercivity of the cell and permit lower intensity magnetic fields to affect the magnetic orientation of the heated SVM cell 101 while not inadvertently affecting unselected and unheated SVM cells.
Movable probes and external heaters are generally not practical for commercial memory applications requiring fast write response times, as there is an inherent latency due to the movement of the heating device. Additional heating conductors and/or heat elements disposed proximate to the SVM cells, though effective, require additional space within the memory device structure as well as requiring additional fabrication processes that likely increase costs.
Heating pulses are typically brief to avoid over-load of the SVM cell and/or the electrical conductors coupled to the SVM cell. Brief heating pulses must additionally elevate the temperature of the SVM cell sufficiently to remain warm during the write operation when the heating pulse is not present. As time is a factor in a write operation, environmental factors may increase the cooling rate of the SVM cell and thus degrade the effectiveness of the heating pulse.
Hence, there is a need for an ultra-high density magnetic memory which overcomes one or more of the drawbacks identified above.